There are many kinds of package manners for packaging a power semiconductor module. In industry products, the package manners are divided according to sealing materials. The commonly-used two package manners are respectively a gel type and a molding type. For both the gel type and the molding type, an electrical signal connection inside the module is achieved by wire bonding (thick aluminum wires are used generally) between electrodes on a top surface of the chip and a circuit pattern of a Direct Bonded Copper (DBC).
Die bonding process is implemented by picking up a chip from a diced wafer via a die bonder, and bonding the chip to a DBC substrate. During the die bonding, both a force and a position of the chip are controllable from picking up the chip by a vacuum nozzle to bonding the chip to the DBC substrate under a controlled pressure, so as to ensure the chip to avoid damage and set at a designed bonded position. The substrate includes a conductive trace and an insulation layer. During the die bonding process for multiple power chips, each chip needs to be bonded to the substrate independently, thereby a distance P between two chips is determined by a bonded position offset W of a single chip and a distance G between the conductive traces. The bonded position offset W is mainly effected by a coating offset of the die-attach (connecting material), a chip bonding offset, and a precision of pattern on the conductive trace of the substrate, and is limited by a precision of the process and a material of the substrate. The manufacture may relate to a common conductive trace which refers to that a plurality of chips are provided on one conductive trace and non-common conductive traces which refer to that a plurality of chips are provided on different conductive traces. FIG. 1 is a cross section schematic view showing two power chips 11 are in the non-common conductive traces when being bonded to a substrate 13 via a die-attach 12, wherein a reference number 14 refers to the conductive traces. FIG. 2 is a plan view corresponding to FIG. 1, wherein a minimum offset W is 0.1 mm, a minimum distance G between the conductive traces is 0.2 mm, therefore, a distance P between two chips whose bottoms are in the non-common conductive traces is at least 0.4 mm (wherein P=2*W+G). FIG. 3 is a cross section schematic view showing two power chips 11 are in the common conductive trace when being bonded to a substrate 13 via a die-attach, wherein bottoms of the two power chips are in the common conductive trace. FIG. 4 is a plan view corresponding to FIG. 3. In order to prevent the chips from contacting with each other, W is at least 0.1 mm, such that the distance P between the chips is at least 0.2 mm (wherein P=2*W).
Therefore, for the power package module of multiple power chips, it is difficult to obtain a relatively small distance between the chips with common conductive trace or non-common conductive traces by the package process at present.